CVE-2024-28956

Advisory lineage Upstream: 0 Downstream: 60
Deferred
Published: 13 May 2025, 21:02
Last modified:03 Nov 2025, 19:29

Vulnerability Summary

Overall Risk (default)
low
23/100
CVSS Score
5.7 MEDIUM
v4.0 (cve.org)
EPSS Score
0.25% LOW
0% probability +0.22%
KEV
Not listed
Ransomware
No reports
Public exploits
None found
Dark Web
Not detected

Timeline

13 May 2025, 21:02
Published
Vulnerability first disclosed
03 Nov 2025, 19:29
Last Modified
Vulnerability information updated

Description

Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

CVSS Metrics

  • v4.0•MEDIUM•Score: 5.7CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:N
  • v4.0•MEDIUM•Score: 5.7CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
  • v3.1•MEDIUM•Score: 5.6CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N

EPSS Trends

Current EPSS score: 0.25%• Percentile: 48%

Techniques & Countermeasures

  • CWE-1421•Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution

    A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.

References (6)